参考文献

1
A. Vladimirescu and S. Liu.
The simulation of MOS integrated circuits using SPICE2.
ERL Memo No. ERL M80/7, Electronics Research Laboratory, University of California, Berkeley, October 1980.

2
T. Sakurai and A. R. Newton.
A simple MOSFET model for circuit analysis and its application to CMOS gate delay analysis and series-connected MOSFET structure.
ERL Memo No. ERL M90/19, Electronics Research Laboratory, University of California, Berkeley, March 1990.

3
B. J. Sheu, D. L. Scharfetter, and P. K. Ko.
SPICE2 implementation of BSIM.
ERL Memo No. ERL M85/42, Electronics Research Laboratory, University of California, Berkeley, May 1985.

4
J. R. Pierret.
A MOS parameter extraction program for the BSIM model.
ERL Memo Nos. ERL M84/99 and M84/100, Electronics Research Laboratory, University of California, Berkeley, November 1984.

5
Min-Chie Jeng.
Design and modeling of deep-submicrometer MOSFETSs.
ERL Memo Nos. ERL M90/90, Electronics Research Laboratory, University of California, Berkeley, October 1990.

6
Soyeon Park.
Analysis and SPICE implementation of high temperature effects on MOSFET.
Master's thesis, University of California, Berkeley, December 1986.

7
Clement Szeto.
Simulator of temperature effects in MOSFETs (STEIM).
Master's thesis, University of California, Berkeley, May 1988.

8
J. S. Roychowdhury and D. O. Pederson.
Efficient transient simulation of lossy interconnect.
In Proc. of the 28th ACM/IEEE Design Automation Conference, San Francisco, June 17-21 1991.

9
A. E. Parker and D. J. Skellern.
An improved FET model for computer simulators.
IEEE Trans CAD, 9(5):551-553, May 1990.

10
Simulation and modeling.
In R. Saleh and A. Yang, editors, IEEE Circuits and Devices, volume 8(3), pages 7-8 and 49. IEEE, May 1992.

11
H. Statz et al.
GaAs FET device and circuit simulation in SPICE.
IEEE Transactions on Electron Devices, 34(2):160-169, February 1987.

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2017-03-27